To increase processor performance, clock frequencies used by microprocessors, often referred to as xe2x80x9cCPUsxe2x80x9d, have increased. Also, as the number of circuits that can be used in a CPU has increased, the number of parallel operations has risen. Examples of efforts to create more parallel operations include increased pipeline depth and an increase in the number of functional units in super-scalar and very-long-instruction-word architectures. As processor performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations, such as power, switching noise, and signal integrity must be taken into account.
Higher frequencies for an increased number of circuits also increase switching noise on the power supply. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to degradation. The switching noise may have a local or global effect. Circuits that create large amounts of noise may be relatively isolated; however, they may also affect other circuits, possibly involving very complex interactions between the noise generation and the function of affected circuits. Thus, providing power to the components in a computer system in a sufficient and timely manner has become an issue of significant importance.
As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock is often sent to help recover the data. The clock determines when the data should be sampled by a receiver""s circuits.
The clock may transition at the beginning of the time the data is valid. The receiver would prefer, however, to have a signal during the middle of the time the data is valid. Also, the transmission of the clock may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1 shows a section of a typical computer system component (10). Data (12) that is xe2x80x98nxe2x80x99 bits wide is transmitted from circuit A (14) to circuit B (16). To aid in the recovery of the transmitted data, a clock composed of a clock signal (18), or CLK, is also transmitted with the data. The circuits could also have a path to transmit data from circuit B (16) to circuit A (14) along with an additional clock (not shown). The clock signal (18) may transition from one state to another at the beginning of the data transmission. Circuit B (16) requires a signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal (18) may have degraded during transmission. The DLL has the ability to regenerate the clock signal (18) to a valid state and to create a phase shifted version of the clock to be used by other circuits, for example, a receiver""s sampling signal. The receiver""s sampling signal determines when the input to the receiver should be sampled.
Delay locked loops are basically first order feedback control systems. As such, the delay locked loop can be described in the frequency domain as having a loop gain and a loop bandwidth. The loop bandwidth is the speed at which a signal completes the feedback loop of the delay locked loop to produce an update (i.e., error signal). Ideally, the DLL should have the highest possible bandwidth so that the clock and data track each other. In other words, the loop bandwidth of a DLL is typically desired to be high in order to be able to quickly correct errors introduced at an input of the DLL. Thus, the loop bandwidth of a DLL determines to a large degree what portion of input error is transmitted to an output of the DLL.
The loop bandwidth is dependent on a charge pump current and a loop filter capacitance. The more filter capacitance, the lower the loop bandwidth. For stability, i.e., a dominant single pole system, the loop bandwidth is set relatively low, which entails using a large loop filter capacitance. In addition, due to the considerable tolerances of the capacitors across process variations, additional capacitance is usually added to ensure that a DLL is stable. However, more capacitance than is actually needed typically ends up being present.
Another performance measure of a DLL, besides input error tracking, is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, the output plus a known phase shift, should track the input. In a repeated output pattern, such as a clock signal, jitter is present when a transition that occurs from one state to another that does not happen at the same time relative to other transitions is said to have jitter. Jitter is a direct result of power supply noise. The amount of power supply noise is related to the amount of capacitance on the power supply, i.e., the more power supply capacitance, the lower the power supply noise. However, after fabrication, due to the considerable tolerances of capacitors, capacitance may be much greater or less than had been designed for prior to fabrication. Also the amount of capacitance that can be placed on the power supply is often limited by area constraints. If the power supply capacitance is insufficient, a DLL""s jitter performance can suffer, and hence, from a design perspective, maximum utilization of area to provide as much power supply noise filter capacitance as possible is necessary. Thus, after a DLL is fabricated, if it is found that the loop bandwidth is much lower than needed, a mask layer may be changed and re-fabricated to remove capacitance from the filter capacitance and add it to the power supply capacitance. In other cases, a designer may have planned ahead for high loop bandwidth, but ended up without enough capacitance for stability, in which case, the designer has to change a mask layer to add capacitance to the loop filter capacitance. Changing a mask layer is a costly and timely process. Thus, there is a need for a post-silicon, i.e., post-fabrication, capacitance adjustment technique to (1) allow the loop filter capacitance to be adjusted in order to find optimal stable loop bandwidth and (2) use unneeded loop filter capacitance for power supply noise filtering in order to reduce jitter. Such a technique would lead to optimal DLL performance.
According to one aspect of the present invention, an integrated circuit comprises: a voltage controlled delay stage responsive to a first signal applied at a first input thereof; and an adjustable capacitance stage comprising a first capacitance disposed between a power supply and the first input and a second capacitance disposed between the power supply and ground, where the first capacitance and the second capacitance are selectively adjustable.
According to another aspect, a delay locked loop adapted to connect to a power supply and ground comprises: a phase detector stage responsive to an input signal; a charge pump stage responsive to the phase detector stage, where the charge pump stage outputs a bias signal; a voltage controlled delay stage responsive to the bias signal; and an adjustable capacitance stage that is selectively controlled to adjust a first capacitance between the power supply and ground and a second capacitance between the power supply and the bias signal.
According to another aspect, an integrated circuit comprises: voltage delay means for delaying a signal, where the voltage delay means is responsive to a bias signal; and adjustable capacitance means for selectively adjusting a first capacitance disposed between a power supply and the bias signal and a second capacitance disposed between the power supply and ground.
According to another aspect, a method for post-silicon adjustment of a delay locked loop comprises: selectively positioning a first capacitance amount between a power supply and a bias signal of the delay locked loop, where the selective positioning of the first capacitance amount occurs by control of at least one switching device; selectively positioning a second capacitance amount between the power supply and ground; and operating the delay locked loop such that the first capacitance amount serves as a loop filter capacitance and the second capacitance amount serves as a power supply noise filter capacitance.
According to another aspect, a method for optimizing a delay locked loop comprises: forming an integrated circuit having a voltage controlled delay stage responsive to a first signal applied at a first input thereof and an adjustable capacitance stage having a first capacitance disposed between a power supply and the first input and a second capacitance disposed between the power supply and ground; and adjusting the first capacitance and the second capacitance to optimize the delay locked loop.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.